Systemverilog for Design [Hardback]A Guide to Using Systemverilog for Hardware Design and Modelingby Stuart Sutherland and Simon Davidmann and Peter Flake
Usually ships within 6 to 8 working days Description of Systemverilog for DesignSystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. This book, "SystemVerilog for Design", addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and interfaces. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. A companion to this book, "SystemVerilog for Verification", covers the second aspect of SystemVerilog.Title Information
Write a review of this book Customer Reviews from Amazon |
Related Categories
|
Shopping basket
